1. Field of the Invention
This invention generally relates to signal networking and, more particularly, to a system and method for minimizing the susceptibility of a signal network to aggressor net timing window overlap.
2. Description of the Related Art
The size, complexity, and operating or switching speeds of semiconductor ICs have increased, while feature geometries have decreased, and interconnect systems for such ICs have dramatically increased in complexity. In many situations these factors have increased the possible impact on timing due to noise resulting from parasitic capacitance within the interconnect system.
As noted in Wikipedia, in a synchronous digital system, data is supposed to move in lockstep, advancing one stage on each tick of the clock signal. This is enforced by synchronizing elements such as flip-flops or latches, which copy their input to their output when instructed to do so by the clock. To the first order, only two kinds of timing errors are possible in such a system. First, a hold time violation may occur, when an input signal changes too quickly after the clock's active transition. Second, a setup time violation may occur when a signal arrives too late, and misses the time when it should advance. The time when a signal arrives can vary due to many reasons—the input data may vary, the circuit may perform different operations, the temperature and voltage may change, and there are manufacturing differences in the exact construction of each part.
One approach that is used to analyze the impact of the parasitic capacitances is to model the interconnect system as an arrangement of nets (interconnections between gate outputs and interconnected gate inputs) inter-coupled with parasitic capacitors. Static Timing Analysis (STA) is used to develop early and late arrival times (timing window) for each relevant net or node. This timing window is enlarged by a worst case assessment of crosstalk noise for both early and late arrival times using noise aware STA. This worst case timing window is used for timing analysis of all paths through the corresponding net and a list of paths that fail timing requirements are provided. In static timing analysis, the word static alludes to the fact that this timing analysis is carried out in an input-independent manner, and purports to find the worst-case delay of the circuit over all possible input combinations.
More explicitly, STA is a method of computing the expected timing of a digital circuit without performing a simulation. High-performance ICs have conventionally been characterized by the clock frequency at which they operate. Gauging the operation of a circuit at a specified speed requires an ability to measure, during the design process, its delay at numerous steps. Moreover, delay calculations must be incorporated into the inner loop of timing optimizers at various phases of design, such as logic synthesis, layout (placement and routing), and in in-place optimizations performed late in the design cycle. While such timing measurements can theoretically be performed using a rigorous circuit simulation, such an approach is liable to be too slow to be practical. Static timing analysis plays a vital role in facilitating the fast and reasonably accurate measurement of circuit timing. The main goal of static timing analysis is to verify that despite these possible variations, all signals will arrive neither too early nor too late, and hence proper circuit operation can be assured. Faster design times are a result of using simplified STA delay models, and a limited consideration of the effects of logical interactions between signals.
Also, since STA is capable of verifying every path, apart from helping locate setup and hold time violations, it can detect other serious problems like glitches, slow paths and clock skew. The critical path is defined as the path between an input and an output with the maximum delay. Once the circuit timing has been computed by one of the techniques below, the critical path can easily be found by using a traceback method. The arrival time of a signal is the time elapsed for a signal to arrive at a certain point. The reference, or time 0.0, is often taken as the arrival time of a clock signal. To calculate the arrival time, delay calculation of all the components in the path is required. Arrival times, and indeed almost all times in timing analysis, are normally kept as a pair of values—the earliest possible time at which a signal can change, and the latest.
Required time is the latest time at which a signal can arrive without making the clock cycle longer than desired. The computation of the required time proceeds as follows. At each primary output, the required times for rise/fall are set according to the specifications provided to the circuit. Next, a backward topological traversal is carried out, processing each gate when the required times at all of its fanouts are known. The slack associated with each connection is the difference between the required time and the arrival time. A positive slack (s) at a node implies that the arrival time at that node may be increased by (s) without affecting the overall delay of the circuit. Conversely, negative slack implies that a path is too slow, and the path must be sped up (or the reference signal delayed) if the whole circuit is to work at the desired speed.
The behavior of an electronic circuit is often dependent on various factors in its environment like temperature or local voltage variations. In such a case either STA needs to be performed for more than one such set of conditions, or STA must be prepared to work with a range of possible delays for each component, as opposed to a single value. If the design works at each extreme condition, then under the assumption of monotonic behavior, the design is also qualified for all intermediate points.
The use of corners in static timing analysis has several limitations. It may be overly optimistic, since it assumes perfect tracking—if one gate is fast, all gates are assumed fast, or if the voltage is low for one gate, it's also low for all others. Corners may also be overly pessimistic, for the worst case corner may seldom occur. In an IC, for example, it may not be rare to have one metal layer at the thin or thick end of its allowed range, but it would be very rare for all 10 layers to be at the same limit, since they are manufactured independently. Statistical STA, which replaces delays with distributions, and tracking with correlation, is a more sophisticated approach to the same problem.
FIG. 1 is a schematic diagram illustrating a timing window associated with a simple logic gate (prior art). As noted above, a timing window is the time during which a net can toggle its logical value. For the net output of a multi-input gate, there can be a set of values during which the net can toggle, as opposed to a single discrete time, thus creating a timing window (TW). The input “a” of the AND gate is changing at 3 ns and the input “b” is changing at 4.5 ns. So the timing window for the output “x” of this AND gate is 3 ns-4.5 ns, which means this net can toggle at any time in this time intervals, depending upon factors such as the process voltage temperature (PVT).
FIGS. 2A and 2B are, respectively, a schematic diagram of a network of victim and aggressor nets, and an associated timing diagram (prior art). Here, as in the figures to follow, the aggressor nets are shown connected to the victim net via parasitic capacitors. The parasitic capacitors are not necessarily circuit components, but represent an AC coupling between nets. The victim net is the AND gate of FIG. 1 with a timing window of 3 to 4.5 ns. The term “timing window” is understood be the range of signal delay through a net, and the terms “timing window” and “delay range” are used interchangeable. A first aggressor net has an output coupled to the victim net, and has a timing window of 2 to 3.5 ns. A second aggressor net has an output coupled to the victim net, and has a timing window of 4 to 5 ns. An “aggressor” is defined as any net that causes a coupled switching net to either slow or hasten its timing window. Alternately, an aggressor net may cause a coupled switching net to incorrectly change its logical value output. A victim net is a switching net being impacted by an aggressor net.
The crosstalk effect between any 2 nets depends upon following factors: 1) the coupling capacitance between the aggressor and victim nets; 2) how fast the aggressor and/or the victim nets are switching; and, 3) the timing window overlap of the aggressor and victim nets. The first two factors are addressed by physically increasing the spacing between aggressor and victim nets, thereby reducing the capacitive coupling, and by upsizing/downsizing the driver of aggressor/victim net to change the transition times of the nets. The problem with the above techniques is that they directly involve changing the cells/nets in the timing critical path, which may change the normal timing (timing without crosstalk) of the critical path, and lead to an iterative design process. However, there has been little discussion in the art addressing the third factor—of minimizing the timing window overlap.
It would be advantageous if net crosstalk could be eliminated by shrinking the timing window overlap between aggressor and victim nets.
It would be advantageous if the timing window overlap could be shrunk without affecting the timing critical path of either the victim or aggressor net.